`timescale 1ns / 1ns

module tb;

   reg [0:7] d;

   reg 	     reset, clk;

   wire [0:7] q, qn,q2,q3,q4;

   integer    c;

   integer    clk_num;
   

   reg [31:0] tmp;
FF100000 dut(d,clk,reset,q,q2);

   always begin
      clk = 1'b0;
      #25;
      clk = 1'b1;
      #25;
   end

   reg [31:0] old;
   reg [4:0]  index;
   reg [31:0] mask;

   initial begin
      if (!($value$plusargs("clk_num=%d",clk_num)))
	clk_num = 3000;

      $display("Number of clk_num = %0d", clk_num);
      
      d = 8'h00;
      
      reset = 1'b0;
      @(posedge clk);
      #1;
      
      reset = 1'b1;
      for(c=0; c < clk_num; c=c+1) begin
	 @(posedge clk);
	 #1;
	 old = tmp;
	 index = (c%128) & 5'd31;
	 mask = (q ? 1 : 0) << index;
	 
	 tmp[index] = q;
	 
	 if(c % 128 == 0) begin
	    $display("LFSR output:  cycle=%d, output=%x\n", c, tmp);
	    d = ~d;
	    tmp= 0;
	 end
      end

      $finish;
   end

endmodule

      
